The present invention relates to a semiconductor memory device capable of operating at a high speed, and more particularly, to a data output control circuit for aligning and controlling a plurality of data output from a semiconductor memory device that operates at a high speed.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage unit. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at a higher speed. In order to provide a faster and more stable operation of semiconductor memory devices, a variety of circuits inside the semiconductor memory devices must be able to operate at a high speed and transfer signals or data between the circuits at a high speed.
A fast operation of the semiconductor memory device can be achieved by executing a plurality of internal operations at a higher speed and increasing signal and data input/output speeds. As an example, a double data rate (DDR) synchronous dynamic random access memory (SDRAM) can achieve a high-speed data transfer by outputting data in synchronization with falling and rising edges of a system clock. Since the DDR SDRAM can input and output two data through one input/output terminal in one cycle of the system clock, its data input/output speed is higher than that of a typical semiconductor memory device. At present, a semiconductor memory device has been proposed which inputs and outputs four data in one cycle of a system clock.
The DDR SDRAM adopts a prefetch operation in order to output data at a high speed. Herein, the prefetch operation refers to an operation to previously store data or commands at a high speed before the data or commands are processed. For example, the DDR SDRAM accesses memory cells and outputs 2-bit data to a data pad in each clock cycle. Such a prefetch operation is referred to as a 2-bit prefetch operation. In addition, a DDR2 SDRAM adopts a 4-bit prefetch operation to access memory cells and output 4-bit data to a data pad in each clock cycle. A DDR3 SDRAM adopts an 8-bit prefetch operation to access memory cells and output 8-bit data to a data pad in each clock cycle. In this way, the data input/output speed must have been increased in order to enable the semiconductor memory device to operate at a high speed in synchronization with a high-frequency clock. Hence, the semiconductor memory device adopts an operation scheme that reads or writes data corresponding to a minimum burst length through each data input/output pad (DQ) in response to one-time read or write command. This scheme is referred to as an N-bit prefetch operation, where N is equal to the minimum burst length.
As described above, since a semiconductor memory device recently proposed is required to input and output four data in one cycle of a system clock, it adopts an 8-bit prefetch operation for high-speed data input/output. Eight data output from unit cells in response to one read command are transferred in parallel through the corresponding sense amplifiers and data input/output lines. The parallel data are serialized in order to output them through one data pad. In order to control such an operation, the semiconductor memory device includes a plurality of data output circuits connected respectively to a plurality of data input/output pads.
FIG. 1 is a block diagram of a data output circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the data output circuit includes a first multiplexer 120, a second multiplexer 140, a latch unit 160, and a third multiplexer 180. The first multiplexer 120 is configured to sequentially output four data D0, D2, D4 and D6, which are output and received in parallel from unit cells, in response to a selection signal SOSEB<2:1>. Hereinafter, the four data D0, D2, D4 and D6 are also referred to as 4-bit data in terms of the number of bits. The second multiplexer 140 is configured to sequentially output the other 4-bit data D1, D3, D5 and D7, which are output and received in parallel from the unit cells, in response to the selection signal SOSEB<2:1>. The latch unit 160 is configured to transfer 4-bit serial data N2, which are received from the second multiplexer 140, in response to a delay locked clock RCLK_DLL. The third multiplexer 180 is configured to sequentially transfer data N1 and N3, which are received respectively from the first multiplexer 120 and the latch unit 160, in response to the delay locked clock RCLK_DLL.
Specifically, data, which are to be transferred in synchronization with rising and falling edges of the delay locked clock RCLK_DLL, are separately transferred to the first multiplexer 120 and the second multiplexer 140. Herein, 4-bit data D0, D2, D4 and D6 transferred to the first multiplexer 120 are output in synchronization with the rising edge of the delay locked clock RCLK_DLL; and 4-bit data D1, D3, D5 and D7 transferred to the second multiplexer 140 are output in synchronization with the falling edge of the delay locked clock RCLK_DLL.
The 4-bit data transferred in parallel to the first and second multiplexers 120 and 140 are serialized by being sequentially output one by one in response to the selection signal SOSEB<2:1>. That is, the 4-bit data input into the first multiplexer 120 are output in the order of D0, D2, D4 and D6; and the 4-bit data input into the second multiplexer 140 are output in the order of D1, D3, D5 and D7. Herein, the selection signal SOSEB<2:1> is generated according to a burst type and a CAS latency CL stored in a mode register set MRS, on the basis of specific address information (e.g., A<2:1>) input together with a read command. That is, the activation time of the selection signal SOSEB<2:1> is determined according to the CAS latency CL, and the value of the selection signal SOSEB<2:1> is determined depending on which of 0 to 7 is a start address and which of a sequential type and a interleave type is a burst type. The data alignment illustrated in FIG. 1 is based on the assumption that the specific address data A<2:1> and A<0> input in response to the read command are all zero.
The latch unit 160 receives the 4-bit serial data N2 from the second multiplexer 140, uses the delay locked clock RCLK_DLL to shift the received 4-bit serial data N2 by 0.5 tCK (i.e., the half cycle of a system clock), and transfers the resulting data to the third multiplexer 180. Finally, the third multiplexer 180 transfers the data N1 received from the first multiplexer 120 in synchronization with a rising edge of the delay locked clock RCLK_DLL, and transfers the data N3 received from the latch unit 160 in synchronization with a falling edge of the delay locked clock RCLK_DLL. As a result, the third multiplexer 180 outputs data MXOUT in the order of D0, D1, D2, D3, D4, D5, D6 and D7 in synchronization with the iterative rising and falling edges of the delay locked clock RCLK_DLL.
FIG. 2 is a waveform diagram illustrating the operation of the semiconductor memory device illustrated in FIG. 1.
Referring to FIG. 2, after the read command is input, the data D0 to D7 are transferred from the time point preceding the CAS latency CL by 0.5 tCK (i.e., the half cycle of an external clock). Thereafter, the transferred data D0 to D7 are serialized in response to the selection signal SOSEB<2:1> and the resulting serial data are output to the outside from the CAS latency CL. Thus, each of the first multiplexer 120 and the second multiplexer 140 in the data output circuit must serialize the 4-bit data, which are input using the selection signal SOSEB<2:1>, within a time period of 0.5 tCK.
As illustrated in FIG. 2, the time for alignment of the first output data D0 among the output data D0 to D7 is smaller in operation margin than the time for alignment of the subsequent output data. As described above, the data output circuit uses the selection signal SOSEB<2:1> to align the data, which are received 0.5 tCK before output to the outside, within a time period of 0.5 tCK. Such an operation is not highly problematic if the operation frequency is not high. As an example, if one clock (i.e., 1 tCK) of the system clock is 1 ns, each of the first multiplexer 120 and the second multiplexer 140 must serialize the 4-bit data within a time period of 0.5 ns. However, the semiconductor memory device is required to operate according to a system clock with a higher frequency, and it is difficult to serialize data within a time period shorter than 0.5 ns, when considering an operation margin of a 4:1 multiplexer MUX used as the first multiplexer 120 and the second multiplexer 140 illustrated in FIG. 1.
Also, if the data output circuit illustrated in FIG. 1 receives the data D0 to D7 earlier than 0.5 tCK before output to the outside (e.g., 1 tCK or 2 tCK before the CAS latency CL), it is impossible to align and output the data D0 to D7 in synchronization with the CAS latency CL. Thus, the semiconductor memory device using the data output circuit illustrated in FIG. 1 has no choice but to have the limit of an operation frequency, and such a structure is not applicable to a semiconductor memory device that operates at a high speed.